1. Field of the Invention
This invention relates to a speed-up technique for a constant di/dt buffer.
2. Brief Description of the Prior Art
Advances in the field of integrated circuit technology have materially increased the speed at which the output of a circuit reacts in response to an input thereto. Such increased speed of operation has resulted in abrupt transitions of the circuit output current.
Though faster circuits are of great value in the art, the abrupt transitions of the output current create inductance problems. This problem is due to the fact that the circuit leads have a small inductance associated therewith and, since voltage is related to the time rate of change of current, these abrupt current transitions create large changes of current at the ground and power supply leads and in the bonding wire, resulting in ground and power supply voltage spikes. These voltage spikes affect the voltages of the devices and cause output ringing, ground bounce and false signals.
In the above noted pending application the above described problems are reduced by causing the voltage from gate to source of an MOS transistor (VGS) minus the transition voltage of the transistor (VT) to vary proportionally to the square root of time in order to achieve a constant di/dt during the turn-on of the MOS transistor. However, this square root of time function is provided after VGS becomes larger than VT, and VGS often does not reach the VT voltage level in a reasonable amount of time, thereby preventing the output from commencing switching until about 2.5 nanoseconds after the input has changed under good operating conditions of strong models, low temperature and high supply voltage. Under poor conditions, the commencement of switching results after about a 7 nanosecond delay or "wait" time, thereby resulting in excessive and unwanted delay before anything happens at the output.
The theory of operation is that, if the current to the circuit output is changed at a constant rate (i.e., di/dt is made a constant), the response obtained is a voltage across the inductance in the package containing the circuit. This voltage across the inductance increases to some value and then stays at that value for a certain time. While the above described circuit operates satisfactorily for the purpose intended, it is apparent that the "wait" time should be decreased and preferably approach theoretical minimum di/dt controlled propagation delay for the ground inductance used.